Because the ceramic medium of chip capacitor is thin and fragile, which makes the production process more difficult and reduces the rate of qualified finished product. Today, let’s introduce a manufacturing method of single layer capacitor - Porous Electrode Method, which can effectively improve the pass rate of the finished chip capacitor, increase the stability of the capacitor, reduce the loss.
In the production process, in order to form an electrode, the ceramic dielectric material is incorporated into a suitable ceramic tape. The ceramic dielectric material burned off during the sintering process, leaving the resultant fired material porous. Typically, this ceramic dielectric material may be graphite, rice starch, finely ground walnut shells, or a host of other organic and inorganic materials. The ceramic tape is formulated so that it is co-fireable with a ceramic dielectric green tape and is compatible after firing as well.
There is one major concern is matching the shrinkages of the electrode and dielectric tapes during sintering and the as-fired thermal coefficients of expansion. Hence, the composition of the ceramic in the rogue material filled tape preferably is similar to the ceramic of the dielectric tape. Thickness of the green dielectric tape is chosen to give the desired end result chip capacitor per unit area and is usually between 0.0005 and 0.005 inch. Thickness of the rogue material filled tape is selected to give the desired capacitor structural integrity and overall fired thickness of the finished chip capacitor.
A co-fireable conductive metal paste is applied to either the dielectric tape or rogue material filled tape, or to both, in most instances by screen-printing. Dielectric and rogue material filled tapes are then laminated by conventional means, encasing the metal paste between them, and then are fired.
After the firing process, the now porous electrode layer precursor is impregnated from its outer surface with conductive metal by processes such as, for example, plating, sputtering and/or osmosis, thus forming an electrical link through pores to the previously applied metal layer and causing the entire “porous” layer to act as an electrode.
At last, the counter electrode is then applied to the opposite outer surface of the dielectric by any of the means mentioned above, and the chip capacitors are diced as may be required.
The single layer capacitor produced by EXSENSE Electronics Technology Co., Ltd. has the advantages of small size, thin thickness(0.15~0.5mm), low equivalent series resistance and low loss. Its application frequency can up to GHz, which is suitable for small or microwave occasion and microwave integrated circuit with functions of blocking direct current, RF by-pass, smoothing, tuning, etc.
Reference Data:
SINGLE LAYER ELECTRONIC CAPACTORS WITH VERY THIN DIELECTRICS AND METHODS TO PRODUCE SAME
US 6, 690, 572 B2
Inventor: Larry A. Liebowitz, 129 Adirondack
Ave. Spotswood, NJ (US) 08884
Notice: Subject to any disclaimer, the term of patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
Appl. No.: 10/090, 816
Filed: Mar. 6, 2002
Prior Publication Data
US 2003/0169555 A1 Sep. 11, 2003
Int. Cl.7 ............................. H01G 4/06; H01G 4/00
U.S. Cl. ............................. 361/311; 361/303
Field of search ............................. 361 /301.4, 303-305, 361/311-313, 320, 321.1-321.5
References Cited
U.S. PATENT DOCUMENTS
3， 689， 810 A * 9/1972 Walles ........................ 361/305
3， 882， 059 A * 5/1975 Elderbaum ................. 29/25.42
5， 254， 360 A *10/1993 Crownover et al. .......... 427/79
5， 737， 180 A * 4/1998 Yoo ............................. 361/313
6， 207， 522 B1 * 3/2001 Hunt et al. .................... 438/393
6， 366， 443 B1 4/2002 Devoe et al. ..................... 361/313
6， 433， 993 B1 * 8/2002 Hunt et al. ..................... 361/303
FOREIGN PATENT DOCUMENTS
P-2000-327964 A * 11/2000
cited by examiner
Primary Examiner - Dean A. Reichard
Assistant Examiner - Eric Thomas
Attorney, Agent or Firm - Leonard Cooper
